Zhipeng Liang
Master's Student, Electronic Systems Engineering
Graduate School of Science and Technology, Kyoto Institute of Technology
I am a master's student in Electronic Systems Engineering at Kyoto Institute of Technology, working on cryogenic CMOS characterization and compact modeling. I built our laboratory's cryogenic measurement environment from the ground up, develop automation tooling for it, and apply machine learning to device compact modeling.
Cryogenic CMOS, characterized and modeled
Two threads run through my work: characterizing and compact-modeling bulk CMOS at cryogenic temperatures, and using machine learning to build device models that stay accurate across a wide dynamic range.
Cryogenic CMOS Characterization & Compact Modeling
Measuring and modeling how bulk CMOS behaves at cryogenic temperatures, with a focus on forward body biasing — from building the measurement environment to silicon-validated compact models.
Machine Learning for Compact Modeling
Using neural networks to build compact device models that stay accurate across many orders of magnitude of transistor current, including a simple blended normalization for wide dynamic range.
Next Questions
The next thread is still forming: new device data, better compact models, and ML methods that make cryogenic CMOS easier to design with.
What is new
- President's Award for Academic Research — Kyoto Institute of Technology
- Excellence Award — AI & Semiconductor Course 2025 Summer (The University of Tokyo)
- Student Paper Award, First Place — IEEE SOCC 2025
- Oral presentation at TAU Workshop 2025 (Seaside, CA, USA)